With improvement in the performance of information processing apparatus, in recent years the data rates of data signals transmitted from the inside and received from the outside of the apparatus have been increased. In a receiver circuit which receives a data signal, an amplitude level of the data signal is decided at a timing to a sampling clock and data recovery is performed on the basis of a decision result. When a data rate is high, a slight deviation of phase between a data signal and a sampling clock has an influence on data detection accuracy. Accordingly, a technique called tracking CDR (Clock and Data Recovery) for detecting such a phase deviation and synchronizing a phase of a sampling clock to a phase of a data signal is used.
A technique called baud rate tracking CDR is known as one of techniques for realizing the tracking CDR. With this technique 1-bit data is sampled once. A technique for calculating an autocorrelation function of a signal sequence obtained by sampling a data signal at a sampling rate which is equal to a transmission baud rate and controlling a sampling phase so as to maximize a calculated value is proposed as an example.
In addition, a technique called 2× tracking CDR is known. With this technique 1-bit data is sampled twice. For example, a technique for preparing a clock other than a data detection clock to detect an edge portion (zero-crossing point) of a data signal and detecting a deviation of phase between the data detection clock and the data signal on the basis of an amplitude level detected by the clock is proposed. The phase deviation is detected with the amplitude level at the zero-crossing point of the data signal as reference. This curbs the influence of variations in the amplitude of a data signal caused by the influence of transmission line loss, noise, or the like on detection accuracy. Accordingly, a phase deviation can be detected with greater accuracy.    Japanese Laid-open Paten Publication No. 02-111130    Japanese Laid-open Paten Publication No. 2002-300142
With a receiver circuit in which the 2× tracking CDR is adopted, a special sampling circuit which samples a data signal by a clock other than a data detection clock is included. That is to say, a special sampling circuit for detecting an amplitude level at a zero-crossing point of a data signal is included, so circuit size increases.